1. Field of the Invention
The present invention relates to techniques for minimizing third order harmonic output signal spurs in architectures having switched current steering elements. More particularly, the present invention comprises an apparatus and method for minimizing harmonic output signal spurs via a set of dummy switches that selectively operate in conjunction with a set of actual switches.
2. Description of the Background Art
An ideal or hypothetical electrical system or circuit may operate upon a set of input signals to generate one or more corresponding output signals having intended or pure spectral content. Real-world electrical systems or circuits, however, produce or generate noise components that may corrupt, interfere with, or distort a desired output signal frequency or frequency band.
Harmonic noise components arise from electrical mixing of frequencies, which causes difference and sum frequencies to appear in an output signal. Such electrical mixing may involve one or more input signal frequencies, as well as one or more frequencies associated with internal circuit operation. Third order harmonic noise components are commonly believed to arise from distortion mechanisms caused by circuit non-linearity. However, third order harmonic noise components may alternatively or additionally imply a dependence upon the states of one or more input signals.
A variety of systems and circuits, such as Digital to Analog Converters (DACs), may include switches that control current steering elements. The current steering elements direct electrical current from one output to another. In a current steering DAC, timing mismatch between activated switches, as well as variations in switch operation or activation sequences as a function of changes in input data over time, contribute to the generation of harmonic output signal noise components.
As input signal frequency, and hence switching frequency, increases, harmonic output signal noise undesirably increases, and Spurious Free Dynamic Range (SFDR) correspondingly degrades. One approach toward minimizing or controlling spurious harmonic output signal noise is through the use of a sample and hold architecture. In a sample and hold architecture, circuit outputs are temporarily disconnected from output signal generating elements at the time at which switching is to occur. After a predetermined settling time has elapsed, the circuit outputs are reconnected to the output signal generating elements, whereupon output signals may be delivered or transmitted. Unfortunately, to ensure error free operation, sample and hold circuitry must operate at twice the speed of the output signal generating elements. This constraint becomes significantly more difficult to meet at higher frequencies.
Another approach toward minimizing harmonic output signal noise is commonly referred to as dynamic element matching. In dynamic element matching, pseudo-random bit sequences selectively determine whether particular switches that were in an on state during a most-recent output signal generation cycle, and which would normally remain in an on state during a next output signal generation cycle, shall be turned off between output signal generation cycles. This results in an averaging of harmonic output signal noise components because different numbers of switches are activated during each output signal generation cycle. Unfortunately, dynamic element matching also results in an increase in a circuit""s noise floor, which reduces the circuit""s dynamic range.
In one embodiment, the present invention comprises a set of activation modules coupled to a set of switch modules. A switch module may comprise an actual driver coupled to an actual switch; and a dummy driver coupled to a dummy switch. An activation module may comprise an actual signal latch, a dummy signal latch, and dummy signal logic.
An activation module may receive signals or bits corresponding to or derived from an incoming signal or data stream, where such incoming signals specify or indicate a next actual state associated with an actual switch. Based upon the current state of an actual switch, the next state of the actual switch, and the current state of a dummy switch associated therewith, the activation module may selectively generate a dummy signal or bit to cause the dummy switch to experience a state transition. In particular, if the current and next states of the actual switch are identical, the dummy signal causes the dummy switch to undergo a state transition. If the current and next states of the actual switch differ, the dummy switch is maintained in its current state.
Taken across multiple switch modules, the present invention may ensure that the total number of switches (i.e., actual switches and dummy switches taken together) that experience state transitions at any given time remains constant. As a result, the present invention may greatly reduce or essentially eliminate a major or dominant contribution to third order spurious harmonic noise.